GloFo readies 14nm RTL to GDSII flow

GloFo, working with Synopsys, Cadence and Mentor, has developed new digital design flows for RTL to GDS implementation for its 14nm finfet process.

Integrated with a technology-proven process design kit (PDK) and early-access standard cell libraries, the flows create a digital design “starter kit” that provides designers with a built-in test case for out-of-the-box physical implementation testing and analysis of performance, power and area.

GloFo’s design flow includes features such as implant-aware placement and double-patterning aware routing, In-Design DRC fixing and yield improvement, local/random variability aware timing, 3D FinFET extraction, and color-aware LVS/DRC sign-off.

The Synopsys-based Design Enablement Starter Kit delivers signed-off GLoFo 14LPP finfet designs.

Cadence and GloFo worked together to create a digital flow for a complete RTL-to-GDSII finfet solution for the 14LPP process.

The 14nm starter kit uses the Mentor Graphics Calibre nmDRC and Calibre MultiPatterning products for layer decomposition, DRC verification and metal filling, while the Calibre nmLVS product is used for logic verification.

GloFo says it is yielding on its 14nm technology and is on schedule to support multiple product tape-outs and volume ramp in 2015.